The statements in this section may serve as a background to help understand the invention and its application and uses, but may not constitute prior art.
Compared with conventional power devices made of silicon, Group III-Nitride (III-N) semiconductors possess a number of excellent electronic properties that enable the fabrication of modern power electronic devices and structures for use in a variety of applications. Silicon's limited critical electric field and relatively high resistance make currently available commercial power devices, circuits, and systems bulky, heavy, with further constraints on operating frequencies. On the other hand, higher critical electric field and higher electron density and mobility of III-N materials allow high-current, high-voltage, high-power, and/or high-frequency performances of improved power transistors that are greatly desirable for advanced transportation systems, high-efficiency electricity generation and conversion systems, and energy delivery networks. For example, with a high breakdown voltage (e.g., >100V) due to large critical electric fields (e.g., 3 MV/cm), and a high-density (e.g., 1013/cm2), high-mobility (e.g., >1200 cm2/Vs) two-dimensional-electron-gas (2 DEG) at the AlGaN/GaN heterojunction, AlGaN/GaN-based high-electron-mobility-transistors (HEMTs) have the potential to greatly reduce power loss and minimize system size of Si-based power electronics.
In spite of the enormous potential of III-N semiconductor structures for producing high-efficiency power electronic devices, device performance improvements are still limited by properties of the semiconductor material, device structures, or fabrication methods. One such limitation that poses a technical challenge for high-voltage HEMT design is electron trapping by surface or bulk trap states, leading to current collapse and an increase of dynamic on-resistance. During switching operations under a high applied voltage, trapped electrons deplete the 2 DEG channel and increases the on-resistance as the applied voltage increases. Drain current levels achievable under high-stress switching are lower than those recorded during DC measurements, and such current collapse translates to lower output power and lower device performance. In addition, although surface traps may be mitigated by surface passivation such as deposition of a dielectric layer, preventing electron trapping on the surface adversely increases the off-state peak electric field at the gate edge and lowers the device breakdown voltage. Instead, field-modulating plates, or field plates, have been proposed in combination of passivation layers to manage electric field, reduce surface trapping, prevent current-collapse, and extend device breakdown voltage.
In general terms, a field plate is an electrode placed over the channel to spread out the electric field and to mitigate peaking of the electric field at the gate edge. Field plates help reduce the maximum electric field, achieve a desirable electrical field profile across the channel, and increase the breakdown voltage of a III-N transistor. The use of multiple field plates further enhances such effects. In a typical lateral field-plate structure, one or more source-connected field plates are formed over a gate contact, between the gate contact and a drain ohmic contact, with increasing field plate lengths, increasing dielectric thickness underneath each field plate, and increasing pinch-off voltage underneath each field plate. The electric field between the gate contact and the drain ohmic contact is spread out by the field plates, extending the breakdown voltage of the device.
Several issues exist for conventional field-plate structures in III-N transistors. First, while dielectric depositions over the gate can separate source field plate, gate field plate, and semiconductor materials in the transistor with appropriate distances, the conventional field-plate structure limits the ranges of separation distances as well as material choices for source and gate field plates. Second, the deposition of one field plate above another often requires the deposition of dielectric materials after gate formation, thus limiting the use of high-temperature processes. Third, the fabrication of conventional field-plate structures becomes increasingly difficult and costly as the number of field plates increases to withstand higher breakdown voltages. Each new field-plate layer on the stack adds an additional set of fabrication steps including dielectric deposition, etching, and metal deposition. Device characteristics also suffer from variations in dielectric thickness and field-plate alignment errors. Although a large number of field plates is desired to better disperse the electric field distribution, increased manufacturing variation and fabrication cost make having more than two or three field plates difficult using the conventional field-plate structure.
Furthermore, in III-N semiconductor devices including those with field-plate structures, reliable and reproducible gold-free ohmic and Schottky metal contacts with low-resistance and good edge acuity are desired. Most low-resistance ohmic contacts in III-N devices use Gold (Au) as a top layer to reduce sheet resistance underneath the ohmic contact region, and to reduce oxidation during high temperature annealing processes. Au-based Schottky contacts are also commonly used in III-N semiconductor devices for their low contact resistances. Nevertheless, the presence of Au in a silicon manufacturing facility such as a fab for large-scale CMOS processing can pose serious contamination concerns that lead to catastrophic yield problems. On the other hand, other materials compatible with CMOS processing either have higher contact resistances, or can not withstand high temperature processing as well as gold.
Therefore, in view of the aforementioned practicalities and difficulties, there is an unsolved need for new and novel field plate geometry and structure designs in semiconductor devices, including III-N semiconductor transistors, with Au-free metal contacts, for better control of device characteristics, simplification of the fabrication process, and advancements in device performance, including the continued scaling of device breakdown voltages. It is against this background that various embodiments of the present invention were developed.